ETH Zurich - Computer Science - Native Systems Group J. Gutknecht

The goal of this project is to develop a massively parallel hardware and software architecture for embedded systems. Our system will rely on a large number of simple interconnected CPUs on an FPGA and on a fully type-safe runtime. A mobile high-performance health monitoring application will serve as a proof of concept.

Lectures

Design of Digital Circuits

Systembau

Technical Reports and Details

The Tiny Register Machine implemented on FPGA.

A DDR SDRAM Interface for Xilinx ML505 Evaluation Platform.

A Bus-Based On-Chip Message Passing Network.

A 12-Core Processor Implementation on FPGA.

A Token-Ring for the TRM.

DDRCH.zip: DDR2 controller for ML505 (The DDR2 controller for Xilinx ML505 board is available. This controller is adapted from the BEE3 DDR2 controller developed by Chuck Thacker.)

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